A basic technological step for manufacturing integrated circuits includes manufacturing an insulating structure for allowing the different electronic components composing the circuit to be electrically separated. A local oxidation step of a silicon substrate should be performed, for a predetermined depth and width, so that the electrical charges generated by the electronic components are limited to very definite substrate areas.
Moreover, there is a general trend in microelectronics to provide a continuous reduction in the size of the different structures forming the integrated circuit. Therefore, the conditions for manufacturing insulating structures become more critical, especially from a geometric and size point of view.
The term STI (Shallow Trench Isolation) indicates a method for manufacturing an insulating structure suitable for technological generations below 0.25 μm. Referring to FIG. 1, the basic steps for manufacturing this kind of insulating structure are summarized below. In particular, a very thin oxide layer 2, called padox, being about 10 nm thick, is grown on a semiconductor substrate 1, whereon a silicon nitride layer 3 is grown, which is typically 100–200 nm thick. The nitride layer 3 serves as a stopping layer for the following planarizing treatments, while the oxide layer 2 is used as a buffer since the nitride layer 3 and the semiconductor substrate 1 have a very different network pitch.
Afterwards, a mask or resist layer 4 is formed on the nitride layer 3 through a traditional photolithographic technique, wherein openings 4′ are defined and the nitride layer 3 and the padox layer 2 are removed in correspondence thereof. Through a following removal step, a trench 5 is then formed in the semiconductor substrate 1 in correspondence with these openings 4′. The trench 5 is formed with vertical walls, as shown in FIG. 2, or with sloping side walls with respect to the semiconductor substrate 1 surface, as shown in FIG. 3.
After etching and subsequently removing the resist mask 4, a CVD (Chemical Vapor Deposition) deposition step fills the trench 5 with a further oxide layer, not shown in the figures, which is then planarized by using CMP (Chemical Mechanical Polishing) technology.
The shape and the features of the trench 5 formed by plasma etching are thus very important. In fact the trench 5 depth, the shape thereof, the cross dimensions, and the roughness of the different surfaces have considerable implications on several parameters. These parameters include the following: the electric insulation effectiveness, the active area quality, the presence or absence of crystallographic dislocations, and the stability of following treatments.
During the semiconductor substrate 1 plasma etching, the resist layer 4 is also slowly removed. If this layer 4 is too thin, after plasma etching the final structure shows a different geometry with respect to the expected geometry, as shown in FIG. 3.
With respect to the STI insulation manufacturing, if the resist mask 4 is not sufficiently thick to mask the nitride layer 3 during the entire etching step for forming the trench 5, the nitride layer could be reduced in thickness. This would lead, after the CMP step and the thickening and wet etching steps, to a different insulating structure from the one obtained with a layer 3 having a completely regular shape of the nitride layer 3 during the entire etching step.
The resist layer 4 provides for a low side resistance to the plasma etching step. A low side resistance involves, during the etching step, a progressive erosion of the resist layer 4 perpendicularly to the etching direction. Subsequently, this leads to a reduction of the cross dimension of the layer 4 which serves to screen the etching.
As shown in FIGS. 4 to 9, the side dimension of the surface being exposed to the etching constantly increases. The areas covered by the resist layer 4 are progressively exposed to plasma and are thus etched. This derives first a sloped side profile of the nitride layer 3 with a subsequent side reduction (often considerable) of the structure final size f in the nitride layer 3 with respect to the starting size I which was to be defined, as evident from FIG. 9.
In the case of Flash memory cells formed by floating gate transistors and formed with an STI insulation, the manufacturing process is modified as shown in FIGS. 10 to 18. Through this process it is possible to form the floating gate region of floating gate transistors without using a supplementary mask, which could cause misalignment problems with the underlying structures. In particular, these figures are sectional views of a Flash memory portion in a perpendicular plane to the floating gate region direction.
The trench 5 is formed in the semiconductor substrate 1, as previously described. Due to the low side resistance of the resist layer 4, the nitride layer 3 formed on the semiconductor substrate 1 has sloped side walls after the etching step of the nitride layer 3, as shown in FIG. 10. In the Flash memory manufacturing process, after filling the trench 5 with an oxide layer 60 to form an insulating region, the nitride layer 3 is removed.
A semiconductor layer 70 called POLY1 is then formed, which is then planarized through CMP, as shown in FIG. 14. The oxide layer 60 is then partially removed to define floating gate regions. Two further layers are then formed. A first insulating layer 80 called ONO is formed, and a semiconductor layer 90 called POLY2 is formed. The entire stack comprising the semiconductor layer 90, the first insulating layer 80 and the semiconductor layer 70 is then etched through a three-step removal process of the layers POLY2/ONO/POLY1 to expose the substrate 1. It is essential that the etching of the POLY1 layer 70 is performed in a chemically selective way with respect to the insulating layer 80 to preserve a very thin gate oxide layer interposed between the POLY1 layer 70 and the semiconductor layer 1, which is not shown in the figures.
Nevertheless, as shown in FIG. 18, after etching the POLY1 layer 70 definite vertical portions 81 of the ONO layer 80 remain, which are indicated with the term “ONO fences”. Since the side walls of the POLY1 layer 70 are not completely vertical, and since the vertical portions 81 are sloping with respect to the semiconductor 1 and they screen, when removing the polysilicon layers 70, 90, a portion of the POLY1 layer 70 thus generates a POLY1 residual 71 with a subsequent short circuit between two adjacent cells.
An important parameter of this memory device manufacturing method, called POLY CMP, is forming a nitride layer 3 whose side profile is vertical. In fact, the side profile of the obtained floating gate regions depends on the nitride layer 3 profile. It even practically takes the same shape thereof.
The problem linked to the low resistance of the resist layer 4, during a plasma removal step of layers underlying this resist layer 4, is more evident the more the memory device size is reduced, such as for example, when using a 193 nm photolithographic technique. In fact, one of the basic features of the photoresist layer being used in the 193 nm photolithographic technique is its low resistance to plasma etching. For the same chemistry being used, the etch rate is generally between 10% and 20% higher than the one being used with traditional photolithographic techniques, such as a 248 nm technique, for example.
This drawback is much more evident when considering the thickness of the resist layer. As the device size decreases, the resist layer should be even thinner to allow reduced-size geometric structures to be focused. For example, the thickness of the resist layer of 5400 Å used in the traditional 248 nm photolithographic technique ranges to a thickness of 3200 Å used in the 193 nm photolithographic technique.
The drawback linked to the low side resistance becomes more critical when etching materials for which a fluoride chemistry (CF4, CH2F2, CHF3, etc.) is required, such as silicon nitride (Si3N4) and silicon oxide (SiO2) layers. In these cases, the etch rate increase is even higher, with values of about 25%–35%.
In the case of an etching step based on a fluoride chemistry, another parameter is very critical: the LER (Line Edge Roughness). Due to the LER, the upper profile of the nitride layer 3, forming the stopping layer, completely rectilinear after the lithography, is turned into a highly ragged profile, as shown in FIGS. 19 and 20.
A first known technical approach to address the above-mentioned problems and meet the need to protect the nitride layer 3 during the plasma etching step of the semiconductor substrate 1 is to interpose an oxide layer 6, called a hard mask, between the nitride layer 3 and the resist mask 4, as shown in FIGS. 21 to 24. Although advantageous under several aspects, this first approach does not succeed in solving the problems linked to the side etch rate and LER, since the etching of the nitride layer 3 is not selective with respect to the hard mask 6.
When two considerably thick layers are to be etched, such as for example, a 600 Å thermal oxide layer 6 and a 1600 Å nitride layer 3, with a necessarily fluorine-based chemistry, the problem of the very low side resistance to the nitride layer etching occurs in a particularly extreme form, even if this layer is protected by an oxide hard mask 6.
The use of the hard mask 6 depends on predetermined factors limiting the use modes of this mask. First of all, the chemistry used in the final part of the semiconductor substrate 1 etching should be selective thereon, otherwise its effectiveness would be limited. Moreover, the hard mask 6 should be formed using a material which can be easily removed (traditionally by wet etching) and without damaging structures which compose the final device. Such a method providing the use of a hard mask is not completely effective.
A further approach for solving the above-mentioned problems provides the use of a hard mask made of a metallic material, such as for example, tungsten, titanium and titanium nitride. In fact, it is possible to selectively etch the silicon nitride layer with respect to the metallic layer. Moreover, the metallic layer can be removed in a wet way.
This approach also has some drawbacks. All the final process steps for forming an electronic device called a frontend should be meticulously preserved from the risk of harmful metallic contaminations for the oxide layers. These oxide layers include the following: HV and LV gate layers, tunnel layer, ONO layer, and active areas, etc. Different technical approaches are involved which considerably increases the manufacturing method complexity.